Gould K20 Logic Analysator
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Modell:
K20
Datum:
1985
Kategorie:
Gruppe:
Beschreibung:
Information
The K20 Logic Analyzer System consists of the K20 Logic
Analyzer unit, the Timing Analysis Data Probe and the
general purpose State Mode Data Probe.
The general purpose State Mode Probe offers 24 bits of data
input with an advanced clocking capability and a substantial
triggering capability for most microprocessor and bus
configurations (both 8 and 16 bits). The Timing Mode Probe
offers complex triggering, sampling rates to 100 MHz, glitch
detection, extremely deep sample memory and sufficient
channels for most jobs, all as standard features.
Because of its considerable sample memory depth, the K20 has
a new feature not previously found in logic analyzers:
Accelerating Rate Scrolling (ARS). ARS allows scrolling
through memory to be slow and precise, or fast, to move to
another point quickly. The rate accelerates as the scrolling
switch continues to be pressed. Releasing the switch
momentarily causes a return to the slower rate. None of the
data are missed during scrolling.
The K20 also offers "Help" messages to lessen reliance on
the User's Manual. The K20 has virtually no limit in terms
of expansion and the addition of Software. The base Analyzer
unit contains the Software required to run the standard data
probes and help messages. Other probes come with Software
and expanded hardware capabilities within the Probe. There
is never a need to open the main unit to add an option.
The K20 Series analyzers which are small and lightweight,
offer a high performance/price ratio. There are only a few,
simple menus. Specific Menus for specialized probes are
included with the Software within the Probe.
Dokumenttyp:
Bedienungsanleitung
Seiten:
70
Größe:
1.88 Mbytes (1974627 Bytes)
Sprache:
english
Revision:
Dokument-ID:
0320-0003-10
Datum:
Qualität:
Gescanntes Dokument, alles ist lesbar.
Upload Datum:
2015 07 30
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Information
1 INTRODUCTION
1.1 USING THE
MANUAL ... 1-1
1.2 INSTRUMENTS DESCRIBED IN THE MANUAL ... 1-2
1.3 Gould K20 SERIES, GENERAL DESCRIPTION ... 1 -3
2 PREPARATION FOR USE, AND SPECIFICATIONS
2.0 Preparation for
use ... 2-1
2.1 Incoming
Inspection ... 2-1
2.2 Return of
Equipment ... 2-1
2.3 Care and Use of the Instrumenjs^..^ ... 2-1
2.4
Specifications ... V:L ... ;:&h ... 2-2
2.5 Timing Mode, 8-Channel Timing
Probe ... 2-2
2.5.1
Memory ... 2-2
2.5.2
Clocks ... 2-4
2.5.3
Triggering ... 2-4
2.5.4 Glitch
Detection ... 2-4
2.5.5 Probe
Inputs ... 2-4
2.6 State Mode, 24-Chan net State
Probe ... 2-5
2.6.1
Memory ... 2-5
2.6.2
Clocks ... 2-5
2.6.3
Features ... 2-5
2.6.4
Triggering ... 2-5
2.6.5 Probe
Inputs ... 2-5
2.7 Physical
Characteristics ... 2-6
3 MENU FORMAT AND CONTROL
3.1 Menu and
Input ... 3-1
3.2 Timing Mode, Clock Source
Menu ... 3-2
3.3 Internal Sample Clock Menu (Timing
Mode) ... 3-3
3.4 Trigger Menu (Timing and
State) ... 3-5
3.5 Timing
Display ... 3-7
3.6 State Mode Clocking
Menu ... 3-8
3.8 State
Display ... 4-1
4.2 Timing, Clock Source
Menu ... 4-2
4.3 Internal Sample Clock
Menu ... 4-3
4.4 Trigger Menu,
Timing ... 4-3
4.5 Timing
Display ... 4-5
4.5.1 Waveform, Trigger, Memory
Map ... 4-5
4.5.2 Number of Channels vs Sample
Rates ... 4-5
4.5.3 Cursor, Time Measurement, Value at
Cursor ... 4-6
4.5.4
ARM-RUN ... 4-6
5 STATE MODE
5.1 Gould K20 Logic Analyzer, State
Mode ... 5-1
5.2 State Mode Clocking Menu and
Overview ... 5-2
5.3 Trigger Menu, State
Mode ... 5-4
5.4 State
Display ... 5-5
5.4.1 Memory
Map ... 5-5
5.4.2
Cursor ... 5-6
5.4.3 ARM-RUN State
Mode ... 5-6
6 GENERAL TOPICS
6.1 Glitch Detection, Timing
Mode ... 6-1
6.2 State Mode Clocking,
Detailed ... 6-2
6-3 State Mode Clocking Example, 6502 Microprocessor 6-4
6.4 State Mode Clocking Example, 8085 Microprocessor 6-9
6.5
Triggering ... 6-12
6.5.1 Triggering
Qualifiers ... 6-12
6.5.2 Trigger
Sequence· ... 6-13
6.5.3 Trigger, Timing
Mode ... 6-13
6.5.4 State Mode
Triggering ... 6-16
6.5.5 Trigger
Delay ... 6-19
6.6 Trigger
Delay ...
■ 6-20
6.7
ARM-RUN ... 6-20
6.8
Reset ... 6-20
7 ANALYSIS EXAMPLES
7.1 Analysis
Examples ... 7-1
7.1.1 Training/Test Card
Description ... 7-1
7.1.2 Connecting Test Leads to the Training/Test
Card ... 7-1
7.2.1 Basic Timing
Analysis ... 7-2
7.2.2 Capturing Sample
Data ... 7-3
7.2.3 Cursor and Time
Measurment ... 7-4
7.2.4
Trigger ... 7-5
7.2.5 Glitch
Detection ... 7-6
7.3.1 Basic State
Analysis ... 7-7
7.3.2 Trigger Menu,
State ... 7-8
8 APPENDIX
8.1
Glossary ... 8-1